حل السؤال الرابع >> اختاروا 5 من القائمة التالية :
كود:
▪ Number of separate conductors
▪ Data width in bits carried simultaneously
▪ Addressing capacity
▪ Lines on the bus are for a single type of signal or
shared
▪ Throughput - data transfer rate in bits per second
▪ Distance between two endpoints
▪ Number and type of attachments supported
▪ Type of control required
▪ Defined purpose
▪ Features and capabilities
Question 5: (3 points)
Do pipelining and superscalar processing techniques affect the number of clock cycles of any individual instruction? Explain your answer.
NO
An instruction fetch-execute
cycle that requires six clock cycles from start to finish will require six clock cycles whether
instructions are performed one at a time or pipelined in parallel with a dozen other
instructions. It is the average instruction cycle time that is improved by performing some
form of parallel execution. If an individual instruction must be completed for any reason
before another can be executed, the CPU must stall for the full cycle time of the first
instruction.